This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory comprising a matrix of six-transistor memory cells.
A prior art CMOS RAM with six-transistor memory cells is disclosed in Ochii et al., "An Ultralow Power 8K.times.8K Bit Full CMOS RAM with a Six-transistor Cell," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, October 1982, (pp. 798-803, FIGS. 3 and 11).
In FIG. 1, a six-transistor memory cell is shown. In that figure, Qp1 and Qn1 are p channel and n channel MOS transistors, respectively, which form a first CMOS inverter, and Qp2 and Qn2 are p-channel and n-channel MOS transistors, respectively, which form a second CMOS inverter. The gate of the first CMOS inverter is connected to the drain of each transistor of the second CMOS inverter, and the gate of the second CMOS inverter is connected to the drain of the first CMOS inverter to form a flip-flop circuit. The source of each p channel MOS transistor Qp1, Qp2 is connected to a voltage source VDD, and the source of each n channel MOS transistor Qn1 and Qn2 is connected to another voltage source VSS. The drains of transistors Qp1 and Qn1, and of transistors Qp2 and Qn2 are set at VDD and VSS potential, respectively, for holding data. For example, when the drains of Qp1, Qn1 are at VDD potential, QP2 is OFF and Qn2 is ON, and then drains of Qp2, Qn2 are at VSS potential, resulting that Qp1 is ON and Qn1 is OFF.
Qn3, Qn4 are n channel MOS transistors which operate as transfer gates. A source of Qn3 is connected to the node of the first CMOS inverter and a source of Qn4 is connected to that of the second CMOS inverter. Bit lines BL1, BL2 are connected to the drain side of transistors Qn3, Qn4, respectively. The gates of Qn3 and Qn4 are connected to word line WL. When Qn3 and Qn4 are ON for memory cell selection and reading and writing, the bit lines BL1, BL2 connected to their drains transmit data to and from the flip flop circuit.
When data is written into this memory cell, e.g., when the drains of the transistors Qp1, Qn1 are set at VSS potential and the drains of Qp2, Qn2 are set at VDD potential, bit line BL1 is at VSS level, BL2 is at VDD level, and Qn3 and Qn4, which operate as transfer gates, are turned ON by word line WL. For read out, on the other hand, bit lines BL1 and BL2 are connected to a sense amplifier (not shown) and then transistors Qn3, Qn4 are turned ON.
The connections between the transistors of the above memory cell are as follows. The gates of Qp1 and Qn1 are formed of GATE 1, which is formed as a unit with a first polycrystalline silicon layer, while the gates of transistors Qp2, Qn2 are formed of GATE 2, which is formed as a unit with the first polycrystalline silicon layer. The source of Qn1 is connected to VSS1 line which is formed of a second polycrystalline silicon layer, and the source of Qn2 is connected to VSS2 line, which is also formed of the second polycrystalline silicon layer. The drains of Qp1 and Qn1 are connected to Al interconnection INTC1, and the drains of Qp2, Qn2 are connected to Al interconnection INTC2. The drains of Qn3 and Qn4 are connected to Al bit lines BL1 and BL2, respectively. As can be seen in FIG. 1, lines VSS1, VSS2, BL1, BL2 and interconnections INTC1 and INTC2 are arranged in the same direction.
The gates of Qn3, Qn4 form the word line WL, which is formed as a unit with the first polycrystalline silicon layer. This word line WL is provided at right angles to the above lines VSS1, VSS2, BL1, BL2 and interconnections INTC1, INTC2. Accordingly, with the prior art memory cell, four Al interconnections (interconnection INTC1, INTC2, bit lines BL1, BL2) are formed on the interlayer insulation layer on the second polycrystalline silicon layer, resulting in a large memory cell pitch width.
Furthermore, with the prior art memory device shown in FIG. 1, one Al VSS3 line, which is, for example, for 8 cells, is provided in the same direction as Al lines INTC1, INTC2, BL1 and BL2. VSS3 line supplies VSS potential to the substrate regions of transistors Qn1, Qn2 formed in the p-well to prevent latch up phenomenon, i.e., to prevent the thyristor effect. For details of this latch up phenomenon refer to "Latch-Up and Image Crosstalk Suppression by Internal Gettering" Constantine N. Anagnostopoulos et al., IEEE Journal of Solid-State Circuits, vol. sc-19, No. 1, February 1984 (pp91-97).
In order to effectively prevent latch up, it is desirable to provide a VSS3 line for each memory cell. If this is done, however, one more Al interconnection is required, increasing the element area required. As a result of this trade off, one VSS3 line was provided for every 8 cells, for example. Accordingly, with the device as a whole, if one more Al interconnection line is required for every 8 cells, increasing the integration of the device is extremely difficult. Also, as only one Al VSS3 line is provided for every eight memory cells, it is impossible to sufficiently increase the resistance to latch up.